1. Field of the Invention
The present invention relates to a semiconductor fabricating process, and particularly to a method of forming an isolation structure.
2. Description of the Prior Art
Since the integrated circuit devices size evolves towards smaller dimensions with increased integration rates, distances and arrangements between devices within a semiconductor substrate are decreasing and become tighter. Therefore, suitable isolation has to be formed between two devices to avoid junction current leakage, and an isolation region has to be reduced in size in order to enhance integration with improved isolation. Among various isolation structures, shallow trench isolations (STIs) have the advantages of a relatively small isolation region, and are accordingly often employed. The conventional STI structure is formed between two metal oxide semiconductor (MOS) transistors and surrounds an active area in the semiconductor substrate to prevent carriers, such as electrons or electric holes, from drifting between two adjacent devices through the substrate which causes junction current leakage. STIs not only isolate such devices effectively but are also inexpensive, which suit semiconductor processes with high integration. Since small isolation regions are desired, trenches formed for forming the STIs are wanted to be narrow. One or more voids tend to be formed after the trench having a high-aspect-ratio profile is filled with isolation material using a high aspect ratio process (HARP). If the trench is filled using a flowable chemical vapor deposition process, the silicon substrate is often over-consumed, resulting in alteration of the active area size. The voids or the size alteration often affects the electric performance of the devices, especially fin field emission transistors (FinFET). Therefore, a novel method is still needed for forming an isolation structure having good qualities.